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   <TITLE>CSE462 VLSI Design</TITLE>
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<H1><BR>
CSE 462: VLSI Design</H1>

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<H3>Professor:</H3>

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<P><!WA0><A HREF="http://www.cse.nd.edu/~jbb/index.html">Dr. Jay Brockman<BR>
</A>384 Fitzpatrick Hall<BR>
phone: 1-8810<BR>
email: <!WA1><A HREF="mailto:jbb@cse.nd.edu">jbb@cse.nd.edu<BR>
</A>office hours: Tu, Th 2:30-3:30, or by appointment</P>
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<H3>Teaching Assistants:</H3>

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<P>Steve Dartt<BR>
email: <!WA2><A HREF="mailto:sdartt@bach.helios.nd.edu">sdartt@bach.helios.nd.edu</A></P>
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<H3>Lecture:</H3>

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<P>Monday, Wednesday, Friday, 117 DeBartolo Hall, 10:40-11:30</P>
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<H3>CAD Lab:</H3>

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<P>Monday, Engineering Computer Cluster, 1:00-2:30<BR>
Tuesday, Engineering Computer Cluster, 7:30-9:00 PM</P>
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<H3>Texts:</H3>

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<P>Required:<BR>
N. Weste and K. Eshraghian<I>. Principals of CMOS VLSI Design, A Systems<BR>
Perspective</I>, 2nd Ed. Addison Wesley, 1993.</P>

<P><BR>
Strongly Recommended:<BR>
Jan M. Rabaey, <I>Digital Integrated Circuits: A Design Perspective</I>,
Prentice Hall, 1996</P>
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<H3>Lecture Notes: </H3>

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<P>Available in class Friday, 8/30. Bring $10 to cover semester xeroxing
fee. </P>
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<H3>Homework Assignments: </H3>

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<P><!WA3><A HREF="http://wizard.cse.nd.edu/class_data/cse462/www/Homework/Homework1.ps">Homework 1</A>: Complementary CMOS Logic/Devices
<B>(Do problems 1-3 only)</B></P>

<P><!WA4><A HREF="http://wizard.cse.nd.edu/class_data/cse462/www/Homework/Homework2.ps">Homework 2</A>: MOS Device Characteristics</P>

<P><!WA5><A HREF="http://wizard.cse.nd.edu/class_data/cse462/www/Homework/Homework3.ps">Homework 3</A>: Inverter DC Performance</P>

<P>Homework 4: Inverter Dynamic Performance</P>

<P><!WA6><A HREF="http://wizard.cse.nd.edu/class_data/cse462/www/Homework/Homework5.html">Homework 5</A>: Physical Design of
Static CMOS Gates</P>

<P><!WA7><A HREF="http://wizard.cse.nd.edu/class_data/cse462/www/Homework/Homework6.ps">Homework 6</A>: Static CMOS Logic Families</P>

<P><!WA8><A HREF="http://wizard.cse.nd.edu/class_data/cse462/www/Homework/Homework7.html">Homework 7</A>: Dynamic Logic</P>
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<H3>Lab/Design Projects: </H3>

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<P><!WA9><A HREF="http://wizard.cse.nd.edu/class_data/cse462/www/Labs/Lab1.ps">Lab 1</A>: Switch-Level Simulation</P>

<P><!WA10><A HREF="http://wizard.cse.nd.edu/class_data/cse462/www/Labs/Lab2.ps">Lab 2</A>: Fabrication Process simulation with
pdFab</P>

<P><!WA11><A HREF="http://wizard.cse.nd.edu/class_data/cse462/www/Labs/Accusim.html">Lab 3</A>: Using Accusim for DC and Transient
Simulation</P>

<P>Lab 4: Inverter Layout (see Custom IC Tutorial in Mentor Bold Browser)</P>

<P><!WA12><A HREF="http://wizard.cse.nd.edu/class_data/cse462/www/Labs/LVS.html">Lab 5</A>: Design Rule and Layout Versus Schematic
Checking</P>

<P><!WA13><A HREF="http://wizard.cse.nd.edu/class_data/cse462/www/Labs/counter.html">Lab 6</A>: Logical Design and Simulation
of an 8-Bit Counter</P>

<P>Lab 7: Counter Layout and Verification</P>

<P>Lab 8: Evaluation of Counter Performance</P>
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<H3>Class newsgroup: <!WA14><A HREF="news:nd.courses.cse462">nd.courses.cse462</A>
<BR>
Web Sites of Related Courses:</H3>

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<P><!WA15><A HREF="http://infopad.EECS.Berkeley.EDU/~icdesign/">Homepage for Jan
Rabaey's new IC design text</A>, with links to lecture notes, CAD tools,
sample problems, projects and more. <BR>
<!WA16><A HREF="http://www-personal.engin.umich.edu/~brown/Eecs427/">University
of Michigan undergrad VLSI Class</A> <BR>
<!WA17><A HREF="http://infopad.eecs.berkeley.edu/~icdesign/FILES/ee141.html">Berkeley's
undergrad VLSI class</A> <BR>
<!WA18><A HREF="http://www-inst.eecs.berkeley.edu/~ee241">Berkeley's advanced
digital integrated circuit class (graduate level)</A> <BR>
<!WA19><A HREF="http://www-leland.stanford.edu/class/ee272/">Stanford's graduate
VLSI class </A></P>
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<H3>Don't Miss:</H3>

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<P><!WA20><A HREF="http://www.mrc.uidaho.edu/vlsi/vlsi.html">University of Idaho
VLSI Links</A></P>
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